Implement RVV integer extension instructions
Implements the integer-extension family from #734.
Adds vzext.vf{2,4,8} and vsext.vf{2,4,8} (V 1.0 §11.3) at the VXUNARY0
decode site, which was previously rejected with a FIXME.
The one non-obvious part is the register-overlap rule. vzext/vsext have
a destination EEW greater than the source EEW, and §5.2 requires the source
EMUL to be at least 1 and the overlap to sit in the highest-numbered
part of the destination group. The spec's own example is that at LMUL=8,
vzext.vf4 v0, v6 is legal while a source of v0, v2 or v4 is not.
That is not what rvv_cross_eew_overlap_illegal() implements — it requires
both groups to share a base register, which matches the narrowing direction
instead and gets these two cases exactly backwards. The check is therefore
spelled out in the execution helper with a comment explaining why the shared
predicate is not used.
Source EMUL is compared against 1 via rvv_lmul_ratio() rather than the
register span, because rvv_eew_reg_span() clamps a fractional EMUL to a
span of one register and the information is lost.
Encodings were checked against riscv-opcodes (funct6=0x12, funct3=0x2,
vs1 = 2..7); reserved vs1 values are rejected. Smoke coverage added to
tests/rvv-smoke.S for vf2/vf4 zero- and sign-extension plus a masked case.
make check passes with EXT_V enabled, and the build was checked in the
default, EXT_V, JIT+EXT_V and EXT_V-without-EXT_F configurations.
clang-format 20.1.7 clean.
Summary by cubic
Implements the integer-extension instructions vzext.vf{2,4,8} and vsext.vf{2,4,8} (V 1.0 §11.3), which were previously rejected as unimplemented. They are now decoded and executed, including masked forms and tail handling; the widening register-overlap rule follows §5.2 rather than the existing rvv_cross_eew_overlap_illegal() predicate.