mlas/arm64: add BF16 fast-math conv kernels for NCHW/NCHWc paths

Merged
MI
7mo ago
+4550-33

Description

Add Arm64 BF16 fast-math convolution support in MLAS:

  • direct NCHW conv
  • depthwise 3x3 NCHWc conv
  • pointwise 1x1 NCHWc conv

This change adds new AArch64 BF16 asm kernels, wires them into MLAS platform dispatch, keeps accumulated pointwise batches on the custom BF16 path instead of falling back to generic SBGEMM, and adds the required BF16 build flags.

The new paths are only used when Arm64 BF16 fast-math is enabled via the existing session option. Baseline FP32 behavior is unchanged.

Performance

Individual convolution improvements when running on c8g AWS instance where in columns base is FP32 execution, fast-math when enabled without this PR and PR is fast-math with this change:

TypeShapefast-math vs basePR w/ fast-math vs basePR w/ fast-math vs fast-math
depthwiseN1 IC32 OC32 H112xW112->112x112 K3x3 S1x1 D1x1 P1/1/1/1 G320.991x1.047x1.057x
depthwiseN1 IC96 OC96 H112xW112->56x56 K3x3 S2x2 D1x1 P1/1/1/1 G961.015x1.015x1.000x
depthwiseN1 IC144 OC144 H56xW56->28x28 K3x3 S2x2 D1x1 P1/1/1/1 G1441.020x1.004x0.984x
depthwiseN1 IC144 OC144 H56xW56->56x56 K3x3 S1x1 D1x1 P1/1/1/1 G1441.034x1.138x1.101x
depthwiseN1 IC192 OC192 H28xW28->28x28 K3x3 S1x1 D1x1 P1/1/1/1 G1920.997x1.033x1.037x
depthwiseN1 IC384 OC384 H28xW28->14x14 K3x3 S2x2 D1x1 P1/1/1/1 G3841.016x1.021x1.005x
depthwiseN1 IC384 OC384 H28xW28->28x28 K3x3 S1x1 D1x1 P1/1/1/1 G3841.011x1.090x1.077x
depthwiseN1 IC576 OC576 H14xW14->7x7 K3x3 S2x2 D1x1 P1/1/1/1 G5761.029x0.995x0.967x
depthwiseN1 IC576 OC576 H14xW14->14x14 K3x3 S1x1 D1x1 P1/1/1/1 G5761.025x1.006x0.982x
depthwiseN1 IC960 OC960 H7xW7->7x7 K3x3 S1x1 D1x1 P1/1/1/1 G9601.002x0.941x0.939x
nchwN1 IC3 OC32 H224xW224->112x112 K3x3 S2x2 D1x1 P1/1/1/1 G11.001x1.058x1.058x
pointwiseN1 IC16 OC96 H112xW112->112x112 K1x1 S1x1 D1x1 P0/0/0/0 G11.213x1.328x1.095x
pointwiseN1 IC32 OC16 H112xW112->112x112 K1x1 S1x1 D1x1 P0/0/0/0 G11.020x1.019x0.998x
pointwiseN1 IC32 OC32 H112xW112->112x112 K1x1 S1x1 D1x1 P0/0/0/0 G11.118x1.196x1.069x
pointwiseN1 IC32 OC144 H56xW56->56x56 K1x1 S1x1 D1x1 P0/0/0/0 G11.220x1.528x1.252x
pointwiseN1 IC32 OC192 H28xW28->28x28 K1x1 S1x1 D1x1 P0/0/0/0 G11.199x1.418x1.183x
pointwiseN1 IC64 OC384 H28xW28->28x28 K1x1 S1x1 D1x1 P0/0/0/0 G11.294x1.938x1.497x
pointwiseN1 IC96 OC32 H56xW56->56x56 K1x1 S1x1 D1x1 P0/0/0/0 G11.080x1.426x1.320x
pointwiseN1 IC96 OC576 H14xW14->14x14 K1x1 S1x1 D1x1 P0/0/0/0 G11.280x1.961x1.532x
pointwiseN1 IC144 OC32 H28xW28->28x28 K1x1 S1x1 D1x1 P0/0/0/0 G11.132x1.351x1.193x
pointwiseN1 IC144 OC32 H56xW56->56x56 K1x1 S1x1 D1x1 P0/0/0/0 G11.073x1.374x1.281x
pointwiseN1 IC160 OC960 H7xW7->7x7 K1x1 S1x1 D1x1 P0/0/0/0 G11.133x1.744x1.539x
pointwiseN1 IC192 OC32 H28xW28->28x28 K1x1 S1x1 D1x1 P0/0/0/0 G11.166x1.411x1.210x
pointwiseN1 IC192 OC64 H28xW28->28x28 K1x1 S1x1 D1x1 P0/0/0/0 G11.212x1.763x1.454x
pointwiseN1 IC320 OC1280 H7xW7->7x7 K1x1 S1x1 D1x1 P0/0/0/0 G11.136x2.059x1.812x
pointwiseN1 IC384 OC64 H28xW28->28x28 K1x1 S1x1 D1x1 P0/0/0/0 G11.256x1.904x1.516x
pointwiseN1 IC384 OC96 H14xW14->14x14 K1x1 S1x1 D1x1 P0/0/0/0 G11.206x1.929x1.600x
pointwiseN1 IC576 OC96 H14xW14->14x14 K1x1 S1x1 D1x1 P0/0/0/0 G11.250x2.055x1.644x
pointwiseN1 IC576 OC160 H7xW7->7x7 K1x1 S1x1 D1x1 P0/0/0/0 G10.902x1.423x1.577x
pointwiseN1 IC960 OC160 H7xW7->7x7 K1x1 S1x1 D1x1 P0/0/0/0 G10.915x1.527x1.668x
pointwiseN1 IC960 OC320 H7xW7->7x7 K1x1 S1x1 D1x1 P0/0/0/0 G11.020x1.756x1.723x
pointwiseN1 IC1280 OC1008 H1xW1->1x1 K1x1 S1x1 D1x1 P0/0/0/0 G10.747x1.149x1.538x

When running the full models the performance improvements are on c8g (AWS Graviton 4) and Standard_D32plds_v6 (Azure Cobalt-100) when running MobileNet v2.7 with 8 threads are:

InstancePR w/ fast-math vs basePR w/ fast-math vs fast-mat
c8g1.892x1.647x
Standard_D32plds_v62.884x1.692x

(cc: @Rohanjames1997 @snadampal)